A common arrangement for low end microcomputer systems places system elements, such as the central processing unit (CPU), main memory (e.g., random access memory, or RAM), read only memory (ROM) and Input/Output (I/O) devices, on the same main bus. Communication on the main bus is through the CPU, an arrangement that can result in unacceptably slow transfer of data (e.g., from an I/O device to RAM). Moreover, devices on the main bus with lower priority, such as I/O devices, face long waits to make data transfers.
In response to these shortcomings, Direct Memory Access (DMA) controllers were developed. A DMA controller connects to the main bus, and is responsible for controlling data signal transfers on the main bus between RAM and I/O devices. To make data transfers, a DMA controller takes control of the main bus when the CPU is not using it (i.e., cycle stealing). Although DMA controllers generally perform adequately, DMA controllers suffer from certain limitations. With a DMA controller, the rate of data transfer is limited by how frequently the CPU allows the DMA controller to gain control of the main bus, and how long the DMA controller can keep control of the main bus. Moreover, DMA controllers are not designed to facilitate data signal transfers between I/O devices: Typically a DMA controller transfers data signals, one word at a time, to or from a particular (i.e., addressed) memory location in RAM.
Another response to the shortcomings of using only the main bus was the mezzanine bus. A mezzanine bus is a second or auxillary bus that is parallel to the main bus, and also is connected to the main bus through a bus to bus interface. The mezzanine bus connects most, if not all, of the I/O devices that would otherwise connect directly to the main bus. In this manner, the I/O devices on the mezzanine bus can transfer data signals between each other without the need to communicate over the main bus. The mezzanine bus includes a bus controller, and may even include a DMA controller.